Field of the Invention
The invention relates to an apparatus for testing a package-on-package semiconductor device and a method for testing the same, and particularly, suitable for testing electrical characteristics and functions of the package-on-package semiconductor device.
Description of the Related Art
With the wide spread use of mobile multimedia products and the urgent requirements for electronic device having higher digital signal processing performance, higher storage capacity, and flexibility demand for, the stacked package on package (PoP) to semiconductor device is growing rapidly.
FIG. 5 schematically shows a general stacked semiconductor package 9. The so-called package-on-package technology means that two or more elements are packaged in a way of vertical stacking or back carrying. As shown in FIG. 5, generally, the package 9 comprises a bottom chip 91 and a top chip 92, wherein the bottom chip 91 is typically an integrated digital or mixed signal logic chip, for example, a baseband process or a multimedia processor, and the top chip 92 is typically an integrated memory chip, for example, DRAM or Flash memory. Accordingly, the advantages of the stacked package reside in compacting the package so as to reduce the whole volume, simplifying the circuitry of the mother board, as compared with the conventional side-by-side package, and improving the frequency performance by the direct connection of a memory chip with a logic circuit.
As to a test process for a general package-on-package semiconductor device, the top chip 92 and the bottom chip 91 are tested, individually, before they are packaged. If the electrical functions of the two chips are verified by the test process functions, then the steps of stacking, wire bonding and packaging are performed to complete a final product. Typically, the test of the electrical functions of the bottom chip 91 has to cooperate with the top memory chip. As such, the test of the bottom chip 91 becomes significantly more complicated, as compared with the test of a single chip.
That is to say, in the conventional test process, the top chip 92 and the bottom chip 91 are aligned up by means of eye estimation, and the test process is performed manually. However, such a test process performed manually would cause a test failure easily due to misjudgment or fault of operation from testing personnel, thereby reducing the test accuracy and consuming costs. Additionally, the efficiency of the manual test can not be promoted further.
It can be seen from the above description of the related art in this industry, there is practically an urgent requirement to accomplish an apparatus for a package-on-package semiconductor device and a test method for testing the same, which can be carried out automatically so as to greatly promote test efficiency and accuracy, that is to say, significantly reduce production costs.